The present invention relates to an adjustment circuit and method thereof, especially to a timing adjustment circuit and method thereof for adjusting timing of transmitting signal as well as timing of receiving signal between chips so as to achieve precise signal transmission between chips and higher reliability of computer system.
Most technical products available now are getting more powerful with compact volume and light weight. This is the result of chips with small size and enhanced performance. Due to high precision of chips, the signal transmission between chips is easy to get interference so that the signal transmission between chips as well as chip performance is also influenced. In order to provide more powerful functions, a single product generally integrates a plurality of chips, such as north bridge and south bridge, on motherboard. Therefore, precise signal transmission becomes one of the major research focuses on development of further technology products.
During signal transmission process between two chips, the chip outputting signal needs an output-end clock signal as output timing for transmitting signal to another chip while the chip receiving signal takes a receiving-end clock signal as receiving timing for receiving signal. Different circuit boards have different wiring layouts, so that chips disposed on different circuit boards have different dispositions. Thus timing of signal transmission between two chips is influenced. Therefore, it is necessary to adjust and match output and receiving timing of chips while arranging chips on circuit boards. The timing adjustment methods available now takes the time, cost and labors in trail and error. That is the technical personnel need to repeat various tests and measurements for adjusting receiving or output timing. However, it's timing consuming and labor intensive. Moreover, the receiving or output timing may not be adjusted to the ideal values due to human errors and thus the signal transmission between chips is unstable.
Moreover, even the receiving and output timing of chips have been adjusted before the circuit boards going out, the wiring and chips on the circuit boards may still be influenced by external factors such as temperature and dust. And further the timing as well as accuracy of signal transmission between chips is affected. In addition, the values of the receiving and output timing are fixed and are difficult to change. Therefore, the reliability of computer system has been influenced.
In order to overcome above problems, the present invention provides a timing adjustment circuit and method thereof that adjust the receiving and output timing automatically. Thus not only human errors caused by manual adjustment are excluded, but also the adjusting time is reduced. The accuracy of adjustment is enhanced for precise signal transmission between chips.